This invention relates generally to microprocessing, and more particularly to providing methods to improve floating point arithmetic operations.
When performing decimal floating point addition, alignment of none, one or both operands must be performed to account for a difference in exponent magnitude. Given that the addition is performed on two numbers with a precision of “p” digits, the resultant sum must also be contained within p digits. Normalization of the resultant sum may be needed if the infinitely precise result exceeds p digits. Alignment of the operands or normalization of the result may be needed depending on the values of the operand's exponents or of the infinitely precise sum.
When two such real decimal floating point numbers are added, they fall into one of three categories. In a first category, the exponents of each operand are equal, and no operand alignment is needed. In a second category, the exponents of each operand are unequal, and alignment of only the operand having the larger exponent is necessary.
In a third category, the exponents of each operand are unequal, and alignment of both operands is necessary. Alignment is required to normalize (i.e., shift left such that the most significant digit is not zero) the operand with the larger exponent, and the other operand is shifted right by a number “n” of digits. The number of digits n by which the other operand is shifted is represented by the equation:n=d−z where “d” is the exponent difference between the operands and “z” is the original number of leading zeroes of the operand having the larger exponent.
In designing a unit which would execute decimal floating point addition instructions in hardware, one must determine to which category the addition operation belongs. The first category, where the operand exponents are equal, is generally the most common. For example, when applied to business transactions, the niche for decimal floating point numbers, one typically adds dollars to dollars, not necessarily dollars to cents. Such “dollar to dollar” operations fall into the first category.
However, while the majority of the first category scenarios are easily determined, there are certain cases which require additional normalization and rounding steps, despite the fact that the operand's exponents are equivalent. Additional steps in a decimal floating point addition operation are thus required to ensure that the operation does not fall into one of these cases. Such additional steps increase the latency and decrease the performance of this most common operation.
The IEEE 754 standard allows for a consistent and uniform way to represent decimal floating point numbers, by breaking down a number into a sign field, an exponent field and a coefficient field.
Decimal floating point numbers may also be represented using the decimal floating point format as specified, e.g., in Chapter 20 of “IBM® z/Architecture Principles of Operation,” Publication No. SA22-7832-05, 6th Edition, April 2007, which is hereby incorporated herein by reference in its entirety. This format breaks down a number into a sign digit (S), a combination field (CF), a biased exponent continuation field (BXCF), and a coefficient continuation field (CCF). Because the exponents of decimal floating point numbers are consistently in the same bit positions, one can extract the exponent of an operand and determine whether an additive operation falls into the first category; if the difference between the exponents is zero, then the operation is in the first category.
Such a method to determine whether an operation falls into the first category suffices for most additive operations and avails itself to trivial hardware implementation; the magnitude of both operations are summed together, and the exponent remains the same. However, there exist cases where, despite the fact that the exponents are equivalent, the addition would cause a carry-out from the prescribed precision. Such an event would require additional hardware checking and adjustments to normalize the resultant magnitude to within the prescribed precision and adjust the exponent by a value of one.
Knowing which addition category the operation belongs to may also be relevant in the event that an external dispatch unit is involved in the design of a microprocessor. If the category is known early in the execution of an addition instruction, then a preemptive signal can be generated to tell the dispatch unit when to issue the next instruction. This is critical to ensure that designs operate close to maximum capacity. For example, knowledge that an additive operation is in the first category will allow the dispatch of the next instruction sooner, thereby increasing performance.
Thus, it would be desirable to be able to reduce the number of checking and normalization steps required in decimal floating point decimal addition. Such a reduction would allow for increased performance, especially for the most common cases.